Comparative Analysis of 1-Bit Adiabatic
Full Subtractor Designed in 45nm Technology

Nikhil Deo; Rusni Kima Mangang

doi:https://doi.org/10.14445/22315381/IJETT-V10P307

Research Article | Open Access | Download PDF

Volume 10 | Number 3 | Year 2014 | Article Id. IJETT-V10P307 | DOI : https://doi.org/10.14445/22315381/IJETT-V10P307

Comparative Analysis of 1-Bit Adiabatic Full Subtractor Designed in 45nm Technology

Nikhil Deo , Rusni Kima Mangang

Citation :

Nikhil Deo , Rusni Kima Mangang, "Comparative Analysis of 1-Bit Adiabatic Full Subtractor Designed in 45nm Technology," International Journal of Engineering Trends and Technology (IJETT), vol. 10, no. 3, pp. 541-544, 2014. Crossref, https://doi.org/10.14445/22315381/IJETT-V10P307

Abstract

This paper presents a comparative analysis of a 1-bit adiabatic full subtractor designed in 45nm technology node. Adiabatic logic is a low power digital circuit design technique which is much more power efficient than CMOS logic. We designed 1-bit full subtractor using 2N2N2P and DCPAL adiabatic logic styles which are two of the popular adiabatic logic styles. We found that the full subtractor designed using DCPAL saves much more power than 2N2N2P adiabatic logic style, also we simulated our circuits at two different frequencies of 100MHz and 300MHz.

Keywords

Adiabatic logic, 2N2N2P, DCPAL, low power

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