The Design of High Speed FIR Filter using Improved DA Algorithm and it’s FPGA Implementation

Magatha Nayak Bhukya; K. Anjaiah; G. Sravya; P. Nagaraju

doi:https://doi.org/10.14445/22315381/IJETT-V3I2P212

Research Article | Open Access | Download PDF

Volume 3 | Issue 2 | Year 2012 | Article Id. IJETT-V3I2P212 | DOI : https://doi.org/10.14445/22315381/IJETT-V3I2P212

The Design of High Speed FIR Filter using Improved DA Algorithm and it’s FPGA Implementation

Magatha Nayak Bhukya, K. Anjaiah, G. Sravya, P. Nagaraju

Citation :

Magatha Nayak Bhukya, K. Anjaiah, G. Sravya, P. Nagaraju, "The Design of High Speed FIR Filter using Improved DA Algorithm and it’s FPGA Implementation," International Journal of Engineering Trends and Technology (IJETT), vol. 3, no. 2, pp. 123-126, 2012. Crossref, https://doi.org/10.14445/22315381/IJETT-V3I2P212

Abstract

when the DA (distributed arithmetic) algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is difficult to achieve the best configuration in the coefficient of FIR filter, the storage resource and the computing speed. According to this problem, the paper provides the detailed analysis and discussion in the algorithm, the memory size and the look-up table speed. Also, the corresponding optimization and improvement measures are discussed and the concrete Hardware realization of the circuit is presented. The design based on Altera EP2C5T144C8 chips is synthesized under the integrated environment of QUARTUS II 7.1. The results of Simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough compared to the traditional FPGA realization.

Keywords

FIR filter, DA algorithm, FPGA.

References

[1] Stanley A. White “Applications of Distributed arithmetic to digital signal processing tutorial review”, IEEE ASSP Magazine 1989.
[2] M. Yamada, and A. Nishihara, “High - Speed FIR Digital Filter with CSD Coefficients Implemented on FPGA”, in Proceedings of IEEE Design Automation Conference, 2001, pp. 7 - 8.
[3] M.A. Soderstrand, L.G. Johnson, H. Arich anthiran, M. Hoque, and R. Elangovan, “Reducing Hardware Requirement in FIR Filter Design”, in Proceedings IEEE International Conference on Acoustics, Speech, and Signal Processing 2000, Vol. 6, pp. 3275 – 3278.
[4] Martinez - Peiro, J. Valls, T. Sansaloni, A.P. Pascual, and E.I. Boemo, “A Comparison between Lattice, Cascade and Direct Form FIR Filter Structures by using a FPGA Bit - Serial DA Implementation”, in Proceedings of IEEE International Conference on Electronics, Circuits and Systems, 1999, Vol. 1,pp . 241 – 244.
[5] A. Croisier, D. J. Esteban, M. E. Levilion, and V. Rizo, “Digital Filter for PCM Encoded Signals”, U.S. Patent No. 3,777,130, issued April, 1973 .
[6] H. Yoo, and D. Anderson, “Hardware - Efficient Distributed Arithmetic Architecture for Hi gh - Order Digital Filters”, in Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005 , Vol. 5, pp. 125 – 128.
[7] H. Chen, C. H. Xiong, S. N. Zhong, “FPGA - based efficient programmable poly phase FIR filter,” Journal of Beijing institute of Technology, 2005, vol. 14, pp. 4 - 8.