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Volume 3 | Issue 4 | Year 2012 | Article Id. IJETT-V3I4P212 | DOI : https://doi.org/10.14445/22315381/IJETT-V3I4P212
Design and Verification of Serial Peripheral Interface
M.Sandya , K.Rajasekhar
Citation :
M.Sandya , K.Rajasekhar, "Design and Verification of Serial Peripheral Interface," International Journal of Engineering Trends and Technology (IJETT), vol. 3, no. 4, pp. 522-524, 2012. Crossref, https://doi.org/10.14445/22315381/IJETT-V3I4P212
Abstract
The objective of th is project is to design SPI Master Core using Verilog and verify the code using system verilog . Serial Peripheral Interface (SPI) is an interface that facilitates the transfer of synchronous serial data . SPI (Serial Peripheral Interface) is a synchronous serial data link that operates in full duplex mode. It communicates in master/slave mode where the master device ini tiates the data frame. Multiple slave devices are allowed with individual slave select line .Serial Peripheral Interface of symmetrical structure can be synthesized using Xilinx 12.3, and then can be simulated using Questa 10.0b. It is a popular interface used for connecting peripherals to each other and to microprocessors. The verification of the project is done using system verilog
Keywords
SPI interface; serial; Verilog HDL; system VeriloReferences
[1] www.opencore.org.Simon Srot. SPI Master Core Specification,Rev.0.6. May 16,2007
[2] Prophet, Graham. Communications IP adds SPI interface to FP - GA. E DN, v 48, n 27, Dec 11, 2003.
[3] Motorola, "MC68HC II manual,".
[4] Smart Computing Dictionary, Serial Peripheral Interface (SPI) (online) http://www.smartcomputing.com/editorial/ dictiona ry/detai l.asp?guid=&searchtype= 1&DicID=12820&RefType=Dictionary (access date 28May 2006)
[5] Frédéric Leens ? An Introduction to I2C and SPI Protocols,IEEE Xplore.
[6] ZHANG Yan - wei, Verilog HDL detailed design procedure, Posts & Telecom Press .
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