Implementation of Power Optimized 2 Bit Polar Decoder Architectures

Badugu Neelima; A.Vijaya Lakshmi

doi:https://doi.org/10.14445/22315381/IJETT-V45P261

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Volume 45 | Number 3 | Year 2017 | Article Id. IJETT-V45P261 | DOI : https://doi.org/10.14445/22315381/IJETT-V45P261

Implementation of Power Optimized 2 Bit Polar Decoder Architectures

Badugu Neelima, A.Vijaya Lakshmi

Citation :

Badugu Neelima, A.Vijaya Lakshmi, "Implementation of Power Optimized 2 Bit Polar Decoder Architectures," International Journal of Engineering Trends and Technology (IJETT), vol. 45, no. 3, pp. 288-294, 2017. Crossref, https://doi.org/10.14445/22315381/IJETT-V45P261

Abstract

There are so many different error correcting codes are existed for the design environment correction. Among those polar codes, as the first provable capacity-achieving codes over binary-input discrete memoryless channel (B-DMC). However, for polar codes, the long latency is a bottleneck for designing. In this paper, a mitigation technique is proposed and adopted to avoid latency drawbacks in polar codes. Maintaining less prone to errors in circuits is very important to avoid data corruption in the system. This paper presents a new built-in 2-D Hamming product code (2–D HPC) scheme to provide reliable operation of polar codes in hostile operating environment applications such as space. Error correction method which in used in this paper is 2-D HPC which can enhances the reliability. By the Simulation waveforms the functionality of the 2-D HPC method which is used for polar codes should be understand with the clear sense. The HDL code is developed with VERILOG language and the synthesis and simulation is done by XILINX ISE EDA Tool.

Keywords

Soft errors, polar codes, Xilinx, Verilog.

References

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