Comparitive Study Of Diffrent Multiplier Architectures

Prashant Kumar Sahu; Prof. Nitin Meena

doi:https://doi.org/10.14445/22315381/IJETT-V4I10P103

Research Article | Open Access | Download PDF

Volume 4 | Issue 10 | Year 2013 | Article Id. IJETT-V4I10P103 | DOI : https://doi.org/10.14445/22315381/IJETT-V4I10P103

Comparitive Study Of Diffrent Multiplier Architectures

Prashant Kumar Sahu , Prof. Nitin Meena

Citation :

Prashant Kumar Sahu , Prof. Nitin Meena, "Comparitive Study Of Diffrent Multiplier Architectures," International Journal of Engineering Trends and Technology (IJETT), vol. 4, no. 10, pp. 4293-4297, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V4I10P103

Abstract

This paper presents a comparative analysis of three different multiplier architectures. The three multipliers architecture are array multiplier, a column bypass multiplier, and a array multiplier using Reversal Logic schemes. The multipliers are implemented on Spartan 6 FPGA. The architectures are compared in terms of critical path delay, power dissipation and area. The different multipliers are compared in terms of dynamic power consumption due to the scaling effects on leakage current. Each of the three multipliers has its own trade-offs between power and delay.

Keywords

Low Power, Multiplier, Switching Delay, bypassing techniques, reversible logic.

References

[1]. Himanshu Thapliyal and M.B Srinivas ”Novel Reversible Multiplier Architecture Using Reversible TSG Gate”, 2006 IEEE.
[2] T. Nishitani, “Micro-programmable DSP chip,” 14th Workshop on Circuits and Systems, pp.279-280, 2001.
[3] V. G. Moshnyaga and K. Tamaru, “A comparative study of switching activity reduction techniques for design of low- power multipliers,” IEEE International Symposium on Circuits and Systems, pp.1560-1563, 1995.
[4] A. Wu, “High performance adder cell for low power pipelined multiplier,” IEEE International Symposium on Circuits and Systems, pp.57–60, 1996.
[5] T. Ahn and K. Choi, “dynamic operand interchange for low power,” Electronics Letters, Vol. 33, no. 25, pp.2118-2120,1997.
[6] J. Choi, J. Jeon and K. Choi, “Power minimization of functional units by partially guarded computation,” International Symposium on Low-power Electronics and Design, pp.131-136, 2000.
[7] J. Ohban, V. G. Moshnyaga, and K. Inoue, “Multiplier energy reduction through bypassing of partial products,” IEEE Asia-Pacific Conference on Circuits and Systems, pp.13–17, 2002.
[8] M. C. Wen, S. J. Wang and Y. M. Lin, “Low power parallel multiplier with column bypassing,“ IEEE International Symposium on Circuits and Systems, pp.1638-1641, 2005.
[9] G. N. Sung, Y. J. Ciou and C. C. Wang, “A power-aware 2- dimensional bypassing multiplier using cell-based design flow,” IEEE International Symposium on Circuits and Systems, pp.3338-3341, 2008.
[10] J. T. Yan and Z. W. Chen, “Low-power multiplier design with row and column bypassing,” IEEE International SOC Conference, pp.227-230, 2009.
[11] Jin-Tai Yan and Zhi-Wei Chen, “low-power multiplier design with row and column bypassing”, department of computer science and information engineering, chung-hua University.