Design of Low Power One - Bit Hybrid - CMOS Full Adder Cells

Sushil B. Bhaisare; Sonalee P. Suryawanshi; Sagar P. Soitkar

doi:https://doi.org/10.14445/22315381/IJETT-V4I5P98

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Volume 4 | Issue 5 | Year 2013 | Article Id. IJETT-V4I5P98 | DOI : https://doi.org/10.14445/22315381/IJETT-V4I5P98

Design of Low Power One - Bit Hybrid - CMOS Full Adder Cells

Sushil B. Bhaisare , Sonalee P. Suryawanshi , Sagar P. Soitkar

Citation :

Sushil B. Bhaisare , Sonalee P. Suryawanshi , Sagar P. Soitkar, "Design of Low Power One - Bit Hybrid - CMOS Full Adder Cells," International Journal of Engineering Trends and Technology (IJETT), vol. 4, no. 5, pp. 1810-1814, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V4I5P98

Abstract

The aim of our work is to evaluate the pe rformanceof One - bit Hybrid full adder cell. To achieve a good - drivability, noise - robustness, and low energy operations f or deep - sub micrometer, we explore Hybrid - CMOS style design. Hybrid - CMOS design styles utilize various CMOS logic style circuit to build new Full Adder with desired performance. This Full Adder is categorized into three modules. We compared the proposed Fu ll Adder cell with conventional static CMOS logic styles Adder Cells like C - CMOS, CPL, TFA, TGA and with some hybrid cells at different Load condition. Each Cell showed different power consumption, Delay, PDP and driving capability. The circuits being studied are optimized for energy efficiency at 0.18um CMOS process Technology.

Keywords

Full Adders, Hybrid CMOS Design style, deep - sub micrometer technology, low power, Delay & PDP

References

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