Design and implementation of DDA architecture for FIR Filters

T. Ranjith Kumar

doi:https://doi.org/10.14445/22315381/IJETT-V4I9P180

Research Article | Open Access | Download PDF

Volume 4 | Issue 9 | Year 2013 | Article Id. IJETT-V4I9P180 | DOI : https://doi.org/10.14445/22315381/IJETT-V4I9P180

Design and implementation of DDA architecture for FIR Filters

T. Ranjith Kumar

Citation :

T. Ranjith Kumar, "Design and implementation of DDA architecture for FIR Filters," International Journal of Engineering Trends and Technology (IJETT), vol. 4, no. 9, pp. 4123-4127, 2013. Crossref, https://doi.org/10.14445/22315381/IJETT-V4I9P180

Abstract

Traditionally, direct implementat ion of a K - tap FIR filter requires K multiply - and - accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity and resource usage. To resolve this issue, we first presen t DA, which is a architecture without multiplier . This pa per implements the DA architecture. This architecture is applicable to only one type of filter Coefficients i.e., fixed filter coefficient. In case if we want to operate on variable filter coefficients we have been using Dynamic Distributed Arith metic (DDA ) Architecture. In this we are provi ding the flexibility to operate on variable filter coefficients. Here also compare DA( Distributed Arithmetic ),D - DA(Decomposed - Distributed Arithmetic ),DDA(Dynamic Distributed Arithmetic) by using of XILINX ISE 9.1.i tool, for simulation and synthesis, dumping on sparton - 3E FPGA.

Keywords

Distributed Arithmetic; FIR; Decomposed DA; dynamic DA.

References

[1] Vhdl programming by J.Baskar.
[2] Distributed Arithmetic for FIR Filter implementation on FPGA by Yajun Zhou , Pingzheng Shi.
[3] Uwe Meyer - Baese.Digital signal processing with FPGA[M]. Beijing:Tsin ghua University Press,2006:50~51
[4] Tsao Y C and Choi K. Area - Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010,PP(99):1~5.
[5] Ch ao Cheng and Keshab K Parhi. Low - Cost Parallel FIR Filter Structures With 2 - Stage Parallelism[J]. IEEE Transactions on Circuits and Systems I : Regular 2007,54(2):280~290.
[6] Tearney G J and Bouma B E. Real - Time FPGA Processing for High - Speed Optical Frequenc y Domain Imaging [J]. IEEE Transactions on Medical Imaging, 2009,28(9):1468~1472.
[7] Hu Guang - shu. Digital signal processing - theory,algorithm and realizes[M]. 2nd ed.Beijing: Tsinghua University Press,2003:296~307.
[8] Chun Hok Ho,Chi Wai Yu and Leong P. Floa ting - Point FPGA: Architecture and Modeling [J]. IEEE Transactions on Very Large Scale Integration Systems, 2008,17(12): 1709~1718.
[9] Evans J B. Efficient FIR filter architectures suitable for FPGA implementation[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing , 2002,41(7):490~493.
[10] Meher P K , Chandrasekaran S and Amira A. FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic [J]. IEEE Transactions on Signal Processing, 20 08,56(7): 3009~3017.
[11] Xia Yu - wen. Digital system design with Verilog[M]. 2nd ed.Beijing:Higher Education Press,2008:102~103.
[12] Sungwook Yu and Swartziander E E. DCT implementation with distributed arithmetic[J]. IEEE Transactions on Computer s, 2001,50(9):985~991.